Demand for semiconductors, wafers, integrated circuits and semiconductor devices (i.e., collectively “semiconductors”) continues to rapidly increase. With the continued market demand, there remain market pressures to increase the number of wafers that can be processed, reduce the geometries of finished wafers and their associated chip footprints, and increase component counts in the reduced geometries. Being able to sustain and meet the market demands with a reliable and consistent offering is a challenge however, in part because wafer manufacture is an environment that is both process sensitive and equipment intensive. Similarly, since wafer fabrication is an expense process, determining as early as possible potential problems or limitations of a planned circuit design are desired.
The fabrication of wafers (i.e., fabrication, fab, or fab environment) is costly and requires advanced processing equipment, unique toolings, and extensive research and testing efforts. Testing of semiconductor devices (i.e., integrated circuits, wafers, or ICs) often includes random but costly electrostatic discharge (ESD) testing on final produced wafers to assess their ability to withstand a planned voltage threshold. In certain situations, an IC and a complement ESD protective circuit are planned to be integrated (i.e., paired) for post-production use. In these pairings, the ESD protective circuit is often designed for a specific voltage threshold and the IC is separately designed for its intended end use. However, in certain cases and more particularly for a multi-voltage IC, though a paired ESD circuit may be a well-designed stand alone protective circuit, when integrated with an IC, the resulting ESD protection to the IC may be non-existent. Unfortunately since failures detected at this stage of testing, at the integration and post-integration level, occur well-after tape out, costs associated with the design and production planning have already been expended. The results of such failures also require further costly design assessment, additional design and pre-production iterative analyses, and continued delays in production. Alternatively, testing of an ESD protective circuit alone has proven ineffective, thereby requiring the IC to be first produced to provide an accurate test result.
It remains widely recognized that ESD as a potential source of damage, especially to semiconductor devices, is a critical and costly matter. ESD events are recognized as a significant contributor of early life failures of a semiconductor device. It is understood that when two objects come in contact with each other, a triboelectric action between them may generate an electrical energy charge that initiates an ESD event. The sudden release of generated charge in an object or person can produce extremely high voltages, currents, and electromagnetic fields that can result in malfunctioning, altering of device parameters, or even destruction of silicon junctions. While there are understood to be a variety of ESD events and types, by example, an ESD event in a human body is believed to generate static charge levels up to 15,000 volts by walking across carpet and up to 5,000 volts by walking across linoleum. Therefore avoiding the production of designs susceptible to ESD damage and inaccurate ESD protective circuit pairing is highly desired.
Accordingly, it is desired to determine an effective pre-production methodology for predicting the efficiency and behavior of a designed ESD protective circuit and testing the ESD protective circuit with a simulated IC. The present invention, in accordance with its various implementations herein, addresses such needs.